Conventional complementary metal oxide semiconductor (CMOS) circuits are inherently susceptible to latchup due to the presence of parasitic bipolar transistors in their construction. See R. S. Muller and T. I. Kamins, DEVICE ELECTRONICS FOR INTEGRATED CIRCUITS, 2nd Edition, John Wiley, 1986. FIG. 1 is a simplified cross-section of a conventional prior art p-type substrate CMOS inverter circuit 6, where the parasitic bipolar transistors are labeled 11-14 and +V.sub.DD is applied at terminal 9 and -V.sub.SS is applied at terminal 10. V.sub.in 15 and V.sub.out 16 are the input and output terminals. Resistors 17 and 18 are the series resistors associated with the parasitic current flow in the substrate 7 and n-type well 8 respectively. N+ source/drain regions 20-21 comprise an N-channel transistor while P+ drain/source regions 23-24 compromise the P-channel transistor. P+ region 22 forms an ohmic substrate 7 contact and N+ region 25 forms an ohmic P-well 8 contact.
Methods for reducing the chance of latchup without altering the recombination properties of the semiconductor crystal include
(1) decoupling the bipolar interaction by dielectric isolation, or PA1 (2) degrading the current gain of the parasitic bipolar transistors. The first approach, while offering total suppression of latchup, involves complicated processing, which makes it impractical. The second approach attempts to reduce parasitic transistor action by manipulating active dopant distributions. The use of dual (twin) wells with epitaxial substrate, and of retrograde wells are some of the most effective dopant schemes. See Muller and Kamins (above) and R. R. Troutman, LATCHUP IN CMOS TECHNOLOGY, Kluwer Academic, 1986.
Parasitic bipolar action also can be minimized by reducing carrier lifetimes around the regions where bipolar action takes place. Lifetime reduction can be achieved by introducing the known "lifetime killer" gold into silicon, or by exposing the devices to neutron irradiation. See W. R. Dawes, Jr., and G. F. Derbenwick, "Prevention of CMOS Latchup by Gold Doping", IEEE Trans Nucl. Sci., NS-23, 2027 (1976). Also see J. R. Adams and R. J. Sokcel, "Neutron Irradiation for Prevention of Latchup in MOS Integrated Circuits", Nuclear and Space Radiation Effects Conf., Jul. 19, 1979. However, gold is a very fast diffuser and cannot be easily localized. The neutron flux is also global for either technique. One adverse effect is an undesired increase in current leakage.
An approach will be detailed that, while degrading the performances of the parasitic bipolar devices, does not affect the electrical performances of the CMOS circuit. It will, in fact, substantially improve the latchup immunity of the circuit.